1. Field of the Invention
The present invention relates to the field of integrated circuits (IC). More specifically, the present invention relates to the generation of clock signals for subsystems on an integrated circuit device.
2. Background Information
Advances in integrated circuit technology have led to the birth and proliferation of a wide variety of integrated circuits, including but not limited to application specific integrated circuits, micro-controllers, digital signal processors, general purpose microprocessors, and network processors. Recent advances have also led to the birth of what""s known as xe2x80x9csystem on a chipxe2x80x9d or SOC. Typically, a SOC includes multiple xe2x80x9ctightly coupledxe2x80x9d subsystems performing very different functions.
Often such subsystems will need to operate asynchronously involving different clock domains. Commonly, the individual subsystems will change operating frequencies depending upon the function the particular sub system is performing. Typically, prior art subsystems have utilized an analog phase locked loop (PLL) to generate the appropriate operating clock frequency based upon an input reference frequency (e.g. provided by the SOC). The outputs of such analog PLLs are usually adjusted by tuning the capacitance on an oscillator to modify the output frequency one way or another. Unfortunately however, analog PLLs do not provide the necessary precision to match the multiplicity of tightly tuned frequency rates required by the subsystems on modern high-speed SOC. Accordingly, over time, frequency drifts result in overruns or packet losses simply due to the rate differentials. The problem is further compounded for the future generations of SOC, where increasing number of subsystems operating in different timing domains have to be integrated on a single IC.
Output from PLLs may also be adjusted using an external divider circuit. However, given an input frequency, conventional dividers do not provide a wide enough range of output frequencies typically necessary for subsystems of an SOC.
Accordingly a need exists to at least partially address these problems to further advance the future generation of SOC.